This invention relates generally to integrated circuit manufacturing and, particularly to chemical mechanical polishing processes for manufacturing integrated circuits.
Integrated circuits are chemically and physically integrated into a substrate such as a silicon or gallium arsenide wafer by patterning layers on a substrate. In particular, semiconductors are formed by providing tungsten or copper wiring or metallization in discrete layers of dielectric films to form a multilayer structure. The metallization is adhered to the dielectric film through a thin liner film comprising tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN). The metallization layer and the liner film are deposited on a patterned dielectric film and then polished, typically by chemical-mechanical planarization (CMP), to expose the dielectric layer.
FIG. 1 shows an example of a preformed semiconductor structure 10 after deposition of the metallization and the liner film and prior to polishing. Generally, to make the semiconductor structure 10, a dielectric layer 12 is deposited on a semiconductor substrate or wafer 11 such as a silicon or gallium arsenide wafer and planarized. The dielectric layer 12 typically contains silicon dioxide (SiO2), borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG). After the surface of the dielectric layer 12 is planarized, it is etched to form a series of trenches (lines) and holes (vias) therein according to a prototype design. For example, FIG. 1 illustrates a trench 13. Thereafter, a thin liner film 14 of tantalum (Ta) and tantalum nitride (TaN) or titanium (Ti) and titanium nitride (TiN) is formed over the etched surface of the dielectric layer including the trenches and holes. A metal such as copper or tungsten is then superimposed over the liner film to form a metallization layer 16 filling the trenches and holes. After the semiconductor structure 10 is formed, the portion of the metallization layer and the liner film that is outside the trenches or holes is removed from the dielectric surface typically by a chemical-mechanical planarization (CMP) process to expose the underlying dielectric layer. Thereafter, the exposed dielectric surface is buffed, i.e., polished or replanarized, to remove any defects such as scratches or embedded particles formed in the dielectric surface during the CMP process.
The CMP process is a well known technique in the semiconductor manufacturing industry. In a typical CMP process, the surface of the semiconductor material to be polished is held against a polishing pad at a predetermined pressure while the polishing pad rotates at a predetermined angular speed. The wafer may also rotate. A polishing slurry is supplied to the interface between the polishing pad and the semiconductor material surface to be polished. Typically, the polishing slurry comprises an abrasive agent such as alumina, silica, or ceria particles for mechanical polishing, and an oxidizing agent at a specific pH for chemically etching or oxidizing the surface of the semiconductor material.
In CMP polishing the semiconductor material 10 illustrated in FIG. 1, the metallization layer 16 is generally removed first followed by the liner film 14. However, where trenches or holes are present in the dielectric film 12, the metallization that overlies the trenches or holes is polished while the liner film 14 outside of the trenches and holes is polished. Because the materials used in the metallization layer 16 and liner film 14 are different, they polish at different removal rates. When the metallization layer 16 is removed at a quicker rate than the liner film 14, overpolishing or dishing occurs in the trenches or holes, which detrimentally affects the performance of the integrated circuit. Alternatively, when the liner film 14 is removed at a faster rate than the metallization layer 16, the dielectric layer will be removed at a faster rate thereby reducing the planarity of the resulting structure.
When copper is used as the material in the metallization layer 16, dishing or overpolishing and dielectric erosion can be serious problems. In particular, copper is typically softer and polishes at a faster rate than the metals used in the liner film 14. Thus, the copper in the trenches or holes is removed at a faster rate than the liner film 14 thus causing dishing or overpolishing as shown in FIG. 2. Furthermore, as shown in FIG. 2, as overpolishing of the copper is taking place in the trenches or holes, a portion of the dielectric film adjacent the trenches or holes can be can be worn away resulting in dielectric erosion.
As is well understood in the art, the formation of planar layers is essential in the production of semiconductor structures. Thus, it is desirable to provide an improved CMP method that provides good planarization without dishing or dielectric erosion.
The present invention is directed to a method for removing a liner film and a metallization layer superimposed over the liner film from the surface of an underlying dielectric layer on a semiconductor wafer. The method comprises at least two steps. In the first step, a first polishing slurry having a plurality of first abrasive particles is used in a chemical mechanical polishing process to remove at least a portion of the metallization layer. In the second step, a second polishing slurry having a plurality of second abrasive particles is used in a chemical mechanical polishing process to remove at least a portion of the liner film. The first abrasive particles and the second abrasive particles have different bulk densities in accordance with the invention.
In a preferred embodiment, the present invention provides a method for removing a copper layer and a liner film from the surface of a dielectric layer on a semiconductor wafer. The method comprises at least two CMP polishing steps. First, at least a portion of the copper layer superimposed over the liner film is removed by a CMP process using a first slurry containing alumina particles as the abrasive agent. Subsequently, a CMP process is employed to remove at least a portion of the liner film using a second polishing slurry containing silica particles having a bulk density that is less than the bulk density of the alumina particles used in the first slurry. The higher bulk density of the abrasive agent in the first step enables the removal of the copper layer at a high speed while the decrease in bulk density in the second step leads to the reduction of the copper polishing rate thus preventing overpolishing of the copper in the metallization trenches or holes and erosion of the dielectric material at the edge of trenches. Thus, the combination of the two separate steps can effectively minimize dishing and erosion without sacrificing the overall speed of the planarization process.
The foregoing and other advantages and features of the invention, and the manner in which the same are accomplished, will become more readily apparent upon consideration of the following detailed description and corresponding drawings, which illustrate preferred and exemplary embodiments of the invention.